Optimization of semiconductor devices continues to be an important goal for the semiconductor industry. The continued miniaturization of semiconductor devices, such as bipolar transistors, presents ongoing challenges to semiconductor manufacturers in maintaining or improving that optimization while minimizing production time and costs. One such challenge resides in the capacitance associated with vertical PNP (VPNP) bipolar transistors that is present due to an isolation region lying under the collector. This capacitance is undesirable because it can adversely affect device speed and overall device performance. Moreover, it has a greater impact as device sizes continue to shrink.
Often, VPNP bipolar transistors are built on a p-type substrate, and the p-type collector of the VPNP is typically isolated from the substrate. One way in which the collector is isolated from the substrate is by an isolation region, often referred to as silicon on insulator (SOI). In some designs, instead of using a bulk silicon wafer, a thin (between 1 and 10 microns) layer of silicon is formed on top of a buried oxide layer. The devices are then created in this top layer. The collector is isolated from the p-substrate by the buried oxide layer on the bottom, and by deep trench isolation on both sides. Unfortunately, this method does not fully address the capacitance issues and is costly as the initial substrates can cost more than double the cost of single bulk silicon wafers. Additionally, the deep trench process requires at least one mask, with several etch steps, a trench fill and one chemical/mechanical polishing (CMP) step.
Another isolation region that is present in VPNP transistors is an n doped isolation region (NISO), which is often used to isolate the collector. The NISO region is typically fabricated by implanting an n-type junction under the collector and is connected to n-doped tubs by adjacent isolation tubs. However, the presence of this NISO region introduces a significant collector-n-isolation capacitance (Ccs), which can adversely affect device speed and performance.
Accordingly, there is a need to provide a process and device by which capacitance can be reduced in a VPNP bipolar transistor without significant productions costs or production time.